1. Field of the Invention
The present invention relates to a semiconductor memory device in which the impurity concentration in a diffusion layer connected to a contact has a high concentration region, and a method of manufacturing the same.
2. Description of the Related Art
A circuit including both a PMOS transistor and NMOS transistor is used in a CMOS device such as a NAND flash memory. Impurity diffusion layers formed in the surface of a semiconductor substrate are used as the source and drain of the transistor. The impurity diffusion layers are formed using an impurity represented by boron in the PMOS transistor, and an impurity represented by arsenic in the NMOS transistor.
The resistance of a contact connected to the impurity diffusion layer has the following problem in the PMOS transistor of the CMOS device.
The diffusion coefficient of boron used in the PMOS transistor is larger than that of arsenic used in the NMOS transistor. To suppress the short-channel effect, therefore, the acceleration energy when implanting boron must be decreased such that a high concentration region of the impurity concentration exists closer to the substrate surface than that in the impurity diffusion layers of the NMOS transistor.
On the other hand, arsenic used in the NMOS transistor is implanted so that the impurity high concentration region exists in a position slightly deeper than the substrate surface, in order to decrease the variation in total amount of impurities implanted into the substrate, and decrease the parasitic resistance between the source and drain of the transistor.
Accordingly, the impurity concentrations in the diffusion layers of the NMOS transistor and PMOS transistor have different the depth of the high concentration region; the impurity high concentration region in the diffusion layer is shallower in the PMOS transistor than in the NMOS transistor.
Under the circumstances, a contact hole to be connected to an upper interconnection layer is formed on the diffusion layer. In this case, in order to ensure the continuity yield between the contact and impurity diffusion layer, overetching is performed in addition to the etching time corresponding to the depth of the contact. Consequently, the surface of the semiconductor substrate is etched at the opening of the contact hole. This sometimes decreases the impurity concentration in the surface at the opening of the contact hole particularly in the PMOS transistor. This decrease in impurity concentration raises the contact resistance between the substrate and contact.
Note that prior art reference information related to the invention of this application is as follows.
[Patent Reference 1] Jpn. Pat. Appln. KOKAI Publication No. 2006-40907